Optimisation and Control of IEEE 1500 Wrappers and User Defined TAMs

With the adoption of the IEEE 1500 [1] Standard, the opportunity exists for System on Chip (SoC) designers to specify test systems in a generic way. As the IEEE 1500 Standard does not address the specification and design of the on-chip Test Access Mechanism (TAM), considerable effort may still be required if test engineers are to optimise testing SoCs with IEEE 1500 Wrapped Cores. This paper describes novel research activity based on the design of TAMs that are compatible with IEEE 1500 wrapped cores and once a Test Resource Partitioning (TRP) scheme has been adopted it is shown that multiple TAM sections and Core Wrappers on a SoC can be controlled through the use of an intelligent test controller. Taking into account previous work on TRP, functional testing using the system bus and TAM architectures, a novel approach is introduced that allows some elements of the system bus to be used as part of the TAM while retaining compatibility with the IEEE 1500 wrapped cores. A small micro-controller SoC design based on the AMBA APB bus is used to investigate this approach. A crucial element of this approach involves interfacing the combined TAM to the mandatory Wrapper Serial Port (WSP) and the optional Wrapper Parallel Port (WPP) of the IEEE 1500 wrapped cores in the chip. Test Application Time (TAT) results are presented that establish the viability of the ideas described, as well as comparative analysis of TAT results derived from a number of test structures based on these techniques.